The present invention relates to an integrated circuit transistor and a method for making it
A three-dimensional MOS transistor of a pillar-like structure is shown and described in a paper titled `A Surrounding Gate Transistor (SGT) Cell for 64/256 Mbit DRAMs`, K. Sunouchi et al, IEDM Technical Digest 1989, pages 23 to 26. According to this structure, the drain region is formed on top of the transistor and the channel region is located below the drain region. In the lower part of the transistor is the source region. In one type of the structure, the source region extends sideways and in the other type it vertically extends in the form of side walls. According to another three-dimensional MOSFET as described in a paper titled `A Fully Depleted Lean-Channel Transistor (DELTA)`, D. Hisamoto et al, IEDM Technical Digest 1989, pages 833 to 836, the drain and source regions of the transistor are formed by a planar structure which is erected on a substrate and the center region of the planar structure is buried under an insulated gate.
One shortcoming of the prior art inherent in the Hisamoto's structure is that since impurities must be doped sideways of the source region high level of precision control is needed to achieve the required impurity profile. In addition, the prior art structures are still not satisfactory to achieve higher level of density.